According to the Heterogeneous Integration Technology Blueprint report released by IEEE, short-term HPC chips are linked to other chips by large-area intermediary layers, embedded bridge carrier boards, small-aperture-ratio silicon through-holes, face-to-face wafer stacking, and hybrid bonding, etc., as illustrated in the following.

• Large Intermediate Layer: This is the mainstream 5D packaging technology for HPC chips. Four HBMs are usually connected through the intermediate layer, but as chip performance continues to increase, a larger intermediate layer will be needed to accommodate up to eight HBMs.
• Embedded Bridge Layer: A bridge layer made of silicon or glass is embedded in the carrier board and bonded to the chip and the carrier board through two side pillars to replace the silicon intermediary layer. The current adopters are Intel's EMIB and Sun Micron's FOCos-Bridge technology [discussed in detail in the previous article:Chiplet Revolutionizing Semiconductor Technology ]. When the placement accuracy is greatly improved, it is expected that the carrier board can be embedded with multiple bridge layers as an alternative to the conventional 5D package.
• Small aperture silicon vias: At present, the depth and width of silicon vias for interlayer silicon is usually 100μm:10μm, while the depth and width of silicon vias for stacked DRAM and logic wafers are 50μm:6μm and 50μm:5μm, respectively. After the introduction of a large number of 3D packaging technologies, the silicon vias have to be continually shrunk in order to increase the density of I/O points. It is estimated that the depth-to-width ratio will remain at 10:1.
• Face-to-face wafer stacking: Currently, the top and bottom wafers are mainly bonded by tin-lead micro bumps. However, in order to increase the density of I/O points, such as Intel's Foveros-Direct technology, a smaller and lower resistance copper pillar is used, which reduces the pitch of the joints up to 10 μm.
• Hybrid Bonding: This is a process in which the metal and oxide mixed interfaces on both sides of the wafer are directly bonded and then allowed to diffusely bond at high temperatures. Because the process mainly uses wafer fabrication equipment, it can reduce the contact spacing to the sub-micron level, and is regarded as the key technology for realizing true 3D packaging. It has been widely used for bonding CMOS image sensors to logic chips and memory, and is being introduced into high-performance computing chip packaging, such as TSMC's SoIC technology.

In addition, the report identifies medium- and long-term technology development directions for advanced packaging for HPC chips, including ultra-fine-pitch carrier boards, wireless on-chip communications, and silicon-photonics solutions, as follows.