As advanced processes in the front-end of semiconductors are approaching their physical limits, the reliance on smaller component sizes to increase their operational capabilities is bound to face rising production costs. The global semiconductor industry is therefore looking to advanced packaging as a key technology to continue the Moore's Law lifecycle, enabling the production of higher-performance wafers with lower power consumption and faster signaling speeds at a lower cost. In the second half of 2024, Fan-Out Packaging (FOPLP) has become the next-generation advanced packaging technology in the spotlight. In addition to TSMC's mention at the conference, FOPLP was also the focus of the Semicon Taiwan 2024 International Semiconductor Expo, and it is also the direction in which packaging and testing and panel makers are trying to lay their groundwork.

Traditional semiconductor packaging is a technology that cuts wafers into chips and then packages them individually. The wafers are connected to the lead frame or substrate through peripheral wire bonding, and as the number of I/O contacts continues to increase, the wire bonding is not enough, which is why it gradually entered the market in the 1990s.