August_Semiconductor|Advanced Packaging Technology for High Performance Computing Chips(Up)
With the transistor size shrinkage gradually approaching the physical limit, resulting in advanced manufacturing process difficulties and lead to rising wafer production costs. For a fab with a capacity of 50,000 wafers per month, it is estimated that the cost of building a fab since the 14nm process will exceed $10 billion, and the cost of a 5nm process fab will increase by 60% to $16 billion. In addition to the significant increase in fab costs, the operation and maintenance costs after mass production are also very alarming. The Center for Security and Emerging Technology (CSET) estimates that the cost of manufacturing each wafer has decreased from $331 for 12/16nm process to $233 for 7nm process, but increased to $238 for 5nm process. This means that the previous method of increasing throughput by reducing wafer size through advanced processes to reduce production costs is no longer applicable, and the performance improvement of transistors has been declining [discussed in more detail in the previous article:Technology Review and Bottlenecks in Semiconductor Development]This means that the semiconductor industry is facing the dilemma of having to invest very high amounts of money in advanced processes but not being able to produce more significant wafers. This means that the semiconductor industry is facing the dilemma of having to invest a very high amount of money in advanced processes, but not being able to produce chips with more significant performance. As a result, some of the R&D centers of semiconductor manufacturers are gradually shifting to advanced packaging to break through the dilemma.